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A DSP platform for function acceleration

The project is self financed by the division of Computer Engineering.


If an instruction-set of a processor is general, the performance is low. If the instruction-set is application specific, the scope of the application is limited. Functional acceleration is therefore essential for most low cost and low power applications.

The main goal

The goal of the project is to design a platform which supports function acceleration. After design of the function acceleration, assembler, RTL code, and simulators will be adapted for the acceleration and the verification on the processor core will not be necessary.

Figure 1: The design flow.

Up to 16 accelerators can be added by users. Up to 64 instructions can be added for function acceleration of the 16 accelerators by users. Users can even add RISC instructions and using register file as operand-A and operand-B.

Up to 61 peripheral and I/O components can be added by users. Three peripheral components (DMA, interrpt controller, and timer) were available peripheral components.

Contact Dake Liu to get more information

Page responsible: Anders Nilsson
Last updated: 2013-09-13