Department of Electrical Engineering (ISY)

NoGAP a Novel Generator of Micro Architecture and Processor Framework

Introduction

The tape out of a new processor is usually the result of a substantial design effort, however by choosing the correct tools the design effort can be eased. When designing a new processor, either a low level RTL language such as Verilog or VHDL or some tool aimed at processor construction using a higher level description language can be used. Both approaches has their advantages and disadvantages, RTL languages offers design freedom but the freedom does not come for free. Overhead is introduced due to micro management of many small details which is an error prone and tedious task requiring substantial verification. The other approach of using a tool made for processor construction has the obvious advantage of hiding complexity but hiding complexity makes it impossible to work with the details if needed therefore the designer gets locked into the architectures supported by the tool.

Every new tool uses abstraction to hide complexity, solid state device physics is abstracted to transistors, transistors to gates, gates to register transfer level, and register transfer level to IP cores and SoC design tools. Abstraction cuts both ways, the very essence of abstraction is to hide complexity, but doing so makes the designer loose control of the underlying system. Complexity can be hidden in many ways, the abstraction chosen might be perfect for a certain task but might induce severe limitations for other tasks. An abstraction is in essence a description language of something else be it symbols, mnemonics, or always statements.

The main assumption made by \nogap{} is that processors are essentially constructed from a number of blocks transforming data according to certain directives. Many functional units together, spread out in both time and space, combines to form more complex tasks, or instructions. The function of a processor is completely defined by its functional units and how they can operate together. This is true for any pipelined micro architecture, it should thus be possible to use the \nogap{} framework even if the micro architecture lacks any form of control path. A processor in this proposal will therefore refer to any pipelined micro architecture.

This project aims to develop a new framework for processor construction. Striking a balance between design freedom and abstraction for micro architecture design.

NoGAP Overview

NoGAP takes the from of a tool chain starting from one of many possible higher level description languages called a facet continuing to a common compiler and ending in a set of other tools, called spawners, producing the actual useful product, this is roughly depicted in the figure below. Each facet produce a description called the NoGAP common language (NoGAP-CL). The NoGAP-CL is compiled to an annotated graph representing the data path. Information for control path construction and instruction coding is also part of the NoGAP-CLC output. The graph also contains information for assembler construction such as where the source and destination operands are in the data path, the exact syntax of the assembler is then up to the assembler spawner. If the user has requested instruction decoders in the NoGAP-CL they are also constructed by the NoGAP-CLC. The output from the NoGAP-CLC is called the NoGAP common description (NoGAP-CD). From the NoGAP-CD the spawners takes on the task of creating assemblers, compilers, functional simulators, cycle accurate simulators and/or a hardware description of the processor.
Figure 1: NoGAP.

Publications

Per Karlström, Dake Liu, NoGAP a Micro Architecture Construction Framework SAMOS IX: International Symposium on Systems, Architectures, MOdeling and Simulation, Samos, Greece, July 2009

Wenbiao Zhou, Per Karlström, and Dake Liu, NoGAPCL: A flexible common language for processor hardware description, DDECS 2010, Vienna Austria. April 2010

Per Karlström, Weibiao Zhou, Dake Liu, Operation classification for control path synthetization with NoGAP, ITNG 2010, April Las Vegas, USA

Wenbiao Zhou, Per Karlström, Dake Liu A Flexible Common Language for Processor Hardware Description IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 14-6 2010, Vienna, Austria

Per Karlström, Faisal Akhlaq, Sumathi Loganathan, Wenbiao Zhou, Dake Liu, Cycle Accurate Simulator Generator for NoGAP, To be published: 2010-09-23, PRIME Asia 2010

Per Karlström, Wenbiao Zhou, Ching-han Wang, Dake Liu, Design of PIONEER: a Case Study using NoGAP, To be published: 2010-09-23, PRIME Asia 2010

Per Karlström, Wenbiao Zhou, Dake Liu, Automatic Port and Bus Sizing in NoGAP, Published: 2010-07-21, Proceedings of SAMOS X

Per Karlström, Sumathi Loganathan, Faisal Akhlaq, Dake Liu, Automatic Assembler Generator for NoGAP, Published: 2010-07-20, PRIME 2010