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FlexFEC: Programmable FEC Processor


The plan of the project is to design a programmable SIMD slave machine for FEC (Forward Error Correction). Flexibilites are specified into two dimentions: 1: decoders of Viterbi, Turbo, Reed-solomon, and LDPC using different algorithms specificed by different specifications. 2: different scale, size, rate, and implementation algorithms

The main goal

The main goal is to design an memory efficient solution based on our experiences in conflict free parallel memory accesses.


Page responsible: Anders Nilsson
Last updated: 2013-09-13