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ASIC-FPGA co-design for ASIC debugging

The project is self financed by the division of Computer Engineering.


A good FPGA designer knows that a good ASIC design may not be that good when implementing it on an FPGA. In this project, we explore methods to design high performance FPGA designs without sacrificing ASIC performance. There are several good reasons for targeting both FPGAs and ASICs:

  • FPGAs are typically used for ASIC verification and emulation. If slower (or smaller) FPGAs can be used here, much is gained.
  • If a system initially designed for an FPGA have to be ported to an ASIC, it makes sense to design the FPGA in such a way that an ASIC port will be efficient.


Andreas Ehliar, Optimizing Xilinx designs through primitive instantiation: Guidelines, techniques, and tips, 7th FPGAworld Conference, September 2010

Olof Andersson, Karl Bengtsson, Adapting an FPGA-optimized microprocessor to the MIPS32 instruction set, Student thesis, Linköpings Universitet, 2010

Daniel Källming, Kristoffer Hultenius, Improving and Extending a High Performance Processor Optimized for FPGAs, Student thesis, Linköpings Universitet, 2010

Jacob Siverskog, Evaluation of partial reconfiguration for FPGA debugging, Student thesis, Linköpings Universitet, 2010

Andreas Ehliar and Dake Liu, An Asic Perspective on FPGA Optimizations, 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, Aug/Sept 2009

Andreas Ehliar, Performance driven FPGA design with an ASIC perspective, Ph.D. thesis, Linköpings Universitet, 2009

Per Karlström, Andreas Ehliar and Dake Liu, High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4 IET Computers & Digital Techniques, Vol. 2, No. 4, pp. 305-313, July 2008

Andreas Ehliar, Aspects of System-on-Chip design for FPGAs, Licentiate thesis, Linköpings Universitet, 2008

Andreas Ehliar, Per Karlström, Dake Liu, A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA, International Conference on Field Programmable Logic and Applications, September 2008

Andreas Ehliar, Dake Liu, An FPGA based Open Source Network-on-chip Architecture, 17th International Conference on Fileld Programmable Logic and Applications, FPL, 2007

Andreas Ehliar, Dake Liu, Thinking outside the flow: Creating customized backend tools for Xilinx based designs, 4th annual FPGAworld Conference, 2007

Andreas Ehliar, Johan Eilert, Dake Liu, A Comparison of Three FPGA Optimized NoC Architectures, Swedish System-on-Chip Conference, SSoCC, 2007

Andreas Ehliar and Dake Liu A Network on Chip based gigabit Ethernet router implemented on an FPGA Proc of the Swedish System-on-Chip Conference (SSoCC), Kolmården, Sweden, May 2006

Andreas Ehliar and Dake Liu Flexible route lookup using range search Proc of the The Third IASTED International Conference on Communications and Computer Networks (CCN), Marina del Rey, CA, USA, Oct 2005

Page responsible: Anders Nilsson
Last updated: 2013-09-13