Some stuff written by Andreas Ehliar

ModelSim related stuff

colorized_signals.tcl A small TCL script for ModelSim that adds a new menu option in the structure window that allows you to add all signals of a module to the wave window and set individual colors on a signal depending on if the signal is an input, output, inout, or an internal signal. See Screenshot 1 and Screenshot 2. This script has some problems with SystemVerilog interfaces and also some problems with VHDL enums if I remember correctly. Otherwise it works very well. If you like this script and would like to use it with SystemVerilog and VHDL, please let me know and I'll try to fix it.
stateenumerate.tcl Another small TCL script for ModelSim that adds a menu option that will create virtual types and functions for you. Very handy if you are debugging state machines and having trouble remembering the numerical value of FSM_STATE_PRECHARGE and the like. See Screenshot 1 and Screenshot 2 for a description of how it works.
search.tcl Improved searching for ModelSim wave window. Not yet cleaned up.

Xilinx related stuff

xdlanalyze.pl A perl script that parses an .xdl or .ncd file from the Xilinx tools and shows some statistics about the design. You can see the resources used by individual resources without having to resynthesize each model by itself. The following example shows what I mean:

$ perl xdlanalyze.pl dafk.xdl
XDLAnalyze V1.1 by Andreas Ehliar <ehliar@isy.liu.se>
Analyzing the file /extra/2006/hw/lab2-4/synthdir/dafk.xdl...................................................
+-------------+--------+--------+--------+-----------+--------+--------+
| Module      |   LUTS |     FF | RAMB16 | MULT18x18 |    IOB |    DCM |
+-------------+--------+--------+--------+-----------+--------+--------+
| /           |     64 |        |        |           |    216 |        |
| cpu         |   5065 |   1345 |     12 |         4 |        |        |
| dma0        |    654 |    254 |      1 |           |        |        |
| dvga        |    816 |    755 |      4 |           |        |        |
| eth3        |   2995 |   2337 |      4 |           |        |        |
| jpg0        |   1682 |    681 |      2 |        13 |        |        |
| leela       |    684 |    552 |      4 |         2 |        |        |
| pia         |      9 |        |        |           |        |        |
| pkmc_mc     |    219 |    122 |        |           |        |        |
| rom0        |    111 |      3 |     12 |           |        |        |
| sys_sig_gen |        |      6 |        |           |        |      2 |
| uart2       |    824 |    346 |        |           |        |        |
| wb_conbus   |    618 |     10 |        |           |        |        |
+-------------+--------+--------+--------+-----------+--------+--------+
| Total       |  13741 |   6411 |     39 |        19 |    216 |      2 |
+-------------+--------+--------+--------+-----------+--------+--------+

Update: It seems like the map tool from ISE 10.1 can give the same kind of information nowadays so there is not much use for this any longer.

PyXDL A much more ambitious project than xdlanalyze, this Python library allows the user to manipulate the XDL file to insert for example a logic analyzer into the design.
fpgaproj.tar.gz (Note: this is a bit dated now, take a look at the PPC405 design further down instead.) The Makefiles I use to synthesize and place and route a Xilinx based FPGA design. It uses XST for synthesis and the Xilinx backend tools for place and route. Originally written for the TSEA02 course.

xil_synt_test.sh A shell script that will synthesize and place and route a Xilinx based FPGA design. This is useful if you have some small design which you want to test without bothering to setup an ISE project or a Makefile for it. Usage example:

$ sh xil_synt_test.sh jpeg_top.v jpeg_dma.v  addrgen.v  dct.v transpose.v 
xil_synt_test.sh V1.0 by Andreas Ehliar <ehliar@isy.liu.se>
The basename is jpeg_top out of jpeg_top.v
testsynthdir already exists, contents is:
design.prj    jpeg_top.bld      jpeg_top_map.ncd  jpeg_top.ngd  jpeg_top.syr       jpeg_top.xdl  xst
design.scr    jpeg_top.drc      jpeg_top_map.ngm  jpeg_top.ngr  jpeg_top.twr       jpeg_top.xpi
jpeg_top.bgn  jpeg_top.lso      jpeg_top.ncd      jpeg_top.par  jpeg_top.unroutes  _ngo
jpeg_top.bit  jpeg_top_map.mrp  jpeg_top.ngc      jpeg_top.pcf  jpeg_top_vhdl.prj  tmpdir
Removing testsynthdir in 5 seconds, press ctrl c if you want to abort
4
3
2
1
Removing testsynthdir
Adding files to testsynthdir/design.prj:
jpeg_top.v jpeg_dma.v addrgen.v dct.v transpose.v 
Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 
                 ...
   lots of output from the toolchain
                 ...

It is also possible to add one UCF file in the above command line.

A reference design for a Virtex 2 Pro FPGA using the PPC405 component but without using the EDK.
I was interested in the behaviour of Xilinx' place and route tool and did some experiments where I varied the timing constraints over a large region.

Misc

simpleinit.c A modified version of simpleinit.c found in the OpenRISC project. This version will make sure that the shell spawned by init will get a controlling terminal.

Interesting links

As an aside, if you are interested in modelsim's tcl interface you can find some information about undocumented features at http://www.doulos.com/knowhow/tcltk/examples/constellation/mti_tcl.pdf.
An interesting place for Linux users that want to use the Xilinx tools is the Gentoo WIKI at http://gentoo-wiki.com/HOWTO_Xilinx.

Links to alternative Makefiles/scripts/etc for building Xilinx projects. (For those who are tired of the ISE GUI)

Last update: 2008-11-13 by ehliar@isy.liu.se