Finished Master Thesis Projects

The following projects were conducted by students pursuing their Master's degree in the division of Computer Engineering. For further details and questions, please contact the supervisor of each project.

2012

• Hybrid floating point modules in FPGA

• Design of a DVB-T Receiver: For SFN on a DSP-Processor

• Development of a Wireless Video Transfer System for Remote Control of a Lightweight UAV

• Synchronization of flywheel position between autonomous devices

• Investigation  of LDPC code in DVB-S2

• Assertion Based Verification on Senior DSP

• Benchmarking of Sleipnir DSP Processor, ePUMA Platform

2011

• Dynamic Partial Reconfigurable

• Adaptation of The ePUMA DSP Platform for Coarse Grain Configurability

• Benchmark of MPEG-2 Video Decoding on ePUMA Multi-core DSP Processor

• Improving an FPGA optimized processor

• Integration testing of the Senior Platform Controller

• A Modular 3D Graphics Accelerator for FPGA

• LTE Uplink Modeling and Channel Estimation

• A GPU for embedded FPGA based systems

2010

• Implementation of Elementary Functions for a Fixed Point SIMD DSP Coprocessor

• Verification and FPGA implementation of a floating point SIMD processor for MIMO processing

• Design and Implementation of a DMA Controller for Digital Signal Processor

• An FPGA implementation of neutrino track detection for the IceCube telescope

• Algorithm and optimization of a novel DSP vector co-processor

• Implementation of CMMB System using Software Defined Radio (SDR) Platform

• A Selection of H.264 Encoder Components Implemented and Benchmarked on a Multi-core DSP Processor

• Improving and Extending a High Performance Processor Optimized for FPGAs

• Laserprojektor

• Evaluation of partial reconfiguration for FPGA debugging

• Adapting an FPGA-optimized  microprocessor to the MIPS32 instruction set

• Balanserad robot

• H.264 Baseline Real-time High Definition Encoder on CELL

• Evaluating and Implementing JPEG XR Optimized for Video Surveillance

• Behaviour modeling of a Digital Video Broadcasting System and the Evaluation of its Equalization Methods

2009

• Design of an FPGA Based JTAG Recorder for use in Production of IPTV Set-Top Boxes

• DSP Platform Benchmarking

• VLSI implementiation of key components in a mobile broadband receiver

• Simulating and Benchmarking of open CL based architecture

• Channel estimation and prediction in 3GPP LTE systems

• Synchronization in 3GPP LTE Systems

• Baseband Signal Processing Analysis of 3GPP LTE Systems

• Bridging of SCSI to SATA and Implementation of a SATA Controller using Virtex-5

• A MIMO Testbed for Broadband Software Defined Radio

2008

• Design of software/hardware for a JPEG-accelerator
• Floating Point Processor for Voice Codec
• Design An MP3 Demo using A Low-Power Audio Processor recently taped out

2007

• SOQPSK-algorithm for modulation and de-modulation on a FPGA

• High Performance Baseband Processing for Advanced Phase-array Radar
• Channel Estimation for Advanced MIMO Communication
• Motion Estimation using Multiprocessor SoC
• Development of NoGAP a Novel Generator of Micro Architecture and Processor Framework
• Real-Time Multitask Threading Control

2006

• Efficient WiMAX Receiver Implementation on A Programmable Baseband Processor
• Implementation of Bluetooth Transceiver Behavioral Model for HW adaptation
• FPGA implementation of Viterbi decoder
• Hardware for positioning applications using software defined radio: High speed interfaces with real-time constraints (2006)
• Behavior modeling of EDGE Baseband Processing (2006)
• FPGA implementation of a packet buffer using off chip DDR memory (2006)
• SW/HW codesign for Automotive Computer Vision (2006)
• HW Acceleration for JPEG2000 Decoder (2006)
• Study and Implementation of an Rasterization Accelerator for Mobile 3D Game
• Design of High-performance DMA Controller for Multi-core Platform (2006)

2005

• Behaviour modeling of Wideband: Code Division Multiple Access (2005)
• Implementation of Bluetooth Baseband Behavioral Model in C Language (2005)
• Fully Integrated and Switched Test environment (FIST) and Automated Testing
• Network Processor Specific Multithreading Tradeoffs (2005)
• Implementation of a Gigabit IP Router on an FPGA Platform Using an On-chip Network (2005)
• Study of CABAC Hardware Acceleration with Configurability in Multi-standard Media Processing (2005)
• Design of Single Scalar DSP based H.264/AVC Decoder (2005)
• 2.4G ~ 10.4G Hz CMOS programmable Frequency Divider (2005)
• Design and Implementation of a Hardware Unit for Complex Division (2005)
• Evaluation of Methodology for Parallel Scheduling (2005)
• Home Automation Using Elvin (2005)
• Design and Implementation of Recording Functionality for an IP-based Set-top Box (2005)
• Full frame 3D snapshot (2005)

2004

• A Multimedia DSP processor design (2004)
• Design of a Core Router Using the SoCBUS On-chip Network (2004)
• Parallel JPEG Processing with a Hardware Accelerated DSP Processor (2004)
• Design and Implementation of a Traffic Model and a Stimuli Generator for OCN SoCBUS Architecture (2004)
• Interfacing an external Ethernet MAC/PHY to a MicroBlaze system on a Virtex-II FPGA (2004)

2003

• Feasibility study: Implementation of a gigabit Ethernet controller using an FPGA (2003)
• A hardware MP3 decoder with low precision floating point intermediate storage (2003)
• Mixed RTL and Gate-level Power Estimation with Low Power Design Iteration (2003)
• Design and construction of modular event detector system (2003)
• Embedded Computer for Space Applications Suitable for Linux (2003)

2002

• Design of Application Specific Microcontroller (2002)
• Benchmarking a DSP processor (2002)
• Construction and implementation of a mobile prototype: The Lovebomb (2002)

2001

• A Domain Specific DSP Processor (2001)