Ongoing Master Thesis Project

Design of High-performance DMA Controller for Multi-core Platform

Project Description:

A high performance DMA controller for multi-core SoC platform is designed. SystemC based transaction level model (TML) is implemented. The DMA controller detects arriving requests, set up DMA transaction tasks, manages queuing of tasks, manipulating address generators, manages data transaction buffers, linking multiple data blocks, and terminates transactions. In special cases, the DMA controller can also handles abnormal situation and sending interrupts to report a failure.

Thesis Abstract:

The DMA(direct memory access) controller is a special component in DSP processor used to offload the data transferring from CPU and improve the data access efficiency in the microprocessor. This paper describes the design and implementation of DMA(direct memory access) device for microprocessor developed using C++ Language and SystemC libraries. The main facts covered within this report are the structure of a microprocessor with embedded DMA, and some interesting points of SystemC and TLM library that are useful for the design and implementation of the system level design. This paper starts with an introduction of the theory of DMA , the structure of the microprocessor and the multicore microprocessor. Next it goes further into the DMA specification discussion. The next chapter is the implementation of DMA and the microsystem, later on in this chapter is an explanation of the SystemC methods I used in the system design. At last, the simulation results of the whole system is presented and analyzed. The utility of the DMA is discussed and calculated. With all these aspects covered in the paper, it is easy for the readers to understand the DMA theory , micro architecture as well as the fundamental knowledge of SystemC.

Keywords:

DMA, DSP structure, Multicore microprocessor, System level design