Informationsansvarig: Dake Liu , firstname.lastname@example.org
Sidan uppdaterades senast: 2007-02-01
The project aims at taking a large step forward for the DSP sub-systems for telecommunications and multimedia by developing new architectures and methods, based on the features of the tasks to be executed in these subsystems.
Tasks running on DSP subsystems are relatively predictable and this is the good opportunity to utilize our knowledge to optimize system architectures. This requires cores specialized for different task classes, memory organization adapted to the actual data structures, and development tools suitable for these new architectures.
The project will be the continuation on our current research; its goal is to elaborate, demonstrate and evaluate our proposed new paradigm for high-performance low-cost parallel DSP signal processing, including instruction set, parallel architecture, programming tools, and applications with demonstrated high performance and low cost solution of a DSP subsystem for an embedded system in telecommunication and multimedia applications.
The Division of Computer Engineering: ASIP (Application Specific Instruction set Processors) and multi-processor research for communications. Publications are:
Dake Liu Embedded DSP Processor Design, Application Specific Instruction set Processors ISBN 9780123741233, Elsevier Inc., Morgan Kaufmann Publishers, July 2008
Anders Nilsson, Eric Tell, and Dake Liu, An 11 mm2, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12?m CMOS, IEEE Journal of Solid-State circuits, 2009, Jan.
Andreas Ehliar, Performance driven FPGA design with an ASIC perspective Linköping Studies in Science and Technology, Dissertations, No. 1237, Linköping, Sweden, February 2009.
Andreas Ehliar, Aspects of System-on-Chip Design for FPGAs, Linköping Studies in Science and Technology, Thesis No. 1371, Linköping, Sweden, June 2008.
Per Karlström, Andreas Ehliar and Dake Liu, High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4 IET Computers & Digital Techniques, Vol. 2, No. 4, pp. 305-313, July 2008
Andreas Ehliar, Per Karlström, Dake Liu , A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA FPL 2008, International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, September 2008
Johan Eilert, Di Wu, Dake Liu, Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC), Shanghai, China, May 2008
Di Wu, Johan Eilert, Dake Liu, A Programmable Lattice-Reduction Aided Detector for MIMO-OFDMA 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC), Shanghai, China, May 2008
Rizwan Asghar, and Dake Liu, Very Low Cost Configurable Hardware Interleaver for 3G Turbo Decoding, IEEE International Conference on Information and Communication Tech. from Theory to Applications (ICTTA), Damascus, Syria, April 2008
Johan Eilert, Di Wu, Dake Liu, Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Las Vegas, NV, USA, April 2008
Qi Wang, Di Wu, Johan Eilert, Dake Liu, Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio, IEEE Wireless Communications & Networking Conference, Las Vegas, NV, USA, April 2008
Anders Nilsson, Eric Tell, and Dake Liu, An 11 mm² 70 mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS. ISSCC, IEEE International Solid-State Circuits Conference, San Francisco, USA, February 2008
The research group onx compiler technology and parallel computing: Code generation for DSP, parallel programming and tools. Publications are:
Jörg Keller, Christoph Kessler, Optimized Pipelined Parallel Merge Sort on the Cell BE. 2nd Int. Workshop on Highly Parallel Processing on a Chip (HPPC-2008) at Euro-Par 2008, Las Palmas de Gran Canaria, Spain, Aug. 2008. In E. Luque et al. (Eds.): Euro-Par 2008 Workshops, Springer LNCS 5415: 127-136, 2009.
Andreas Leha, Mikhail Chalabine, Christoph Kessler. Parallelizing Scientific Code with Invasive Interactive Parallelization - A Case Study with Reuseware. Proc. Int. Workshop on Component-Based High Performance Computing (CBHPC-2008), Oct. 2008.
Morgan Ericsson, Welf Löwe, Christoph Kessler, Jesper Andersson. Composition and Optimization. Proc. Int. Workshop on Component-Based High Performance Computing (CBHPC-2008), Oct. 2008.
Christoph W. Kessler, Jörg Keller: Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE. Proc. MCC-2008 First Swedish Workshop on Multicore Computing, Ronneby, Sweden, Nov. 2008.
Kristian Stavåker, Peter Fritzson, Christoph Kessler. Automatic Parallelization of Simulation Code for Equation-based Models with Software Pipelining and Measurements on Three Platforms. Håkan Lundvall, MCC-2008 First Swedish Workshop on Multicore Computing, Ronneby, Sweden, Nov. 2008.
The Division of Communication Systems: MIMO wireless communications, receiver signal processing, resource allocation in wireless networks, and cognitive radio.
The Division of Information Coding: Information coding, and robust video transmission over Internet.
The Embedded Systems Laboratory: Design and test of embedded and real-time systems.
M. Bao, A. Andrei, P. Eles, Z. Peng, An Energy Efficient Technique for Temperature-Aware Voltage Selection, Technical reports in Computer and Information Science, Linköping University Electronic Press.
M. Bao, A. Andrei, P. Eles, Z. Peng, On-line Thermal Aware Dynamic Voltage Scaling for Energy Optimization with Frequency/Temperature Dependency Consideration. Proc. Design automation Conference (DAC), San Francisco, California, July 26-31, 2009 .