In contrast to general purpose microprocessors, ASIP give much higher performance, lower power, and lower silicon costs because of the optimized application specific instruction set and microarchitecture.
ASIP research is a challenging area. The required knowledge for ASIP research is broad, ranging from applications, architecture selection, code compiling, parallel programming, microarchitecture, down to silicon fabrication. Our research demonstrates state-of-the-art ASIP concept designs. Our main academic interests include exploration of extreme performance with specific flexibility, low silicon cost, and low power architectures.
We focus on DSP (digital signal processor) and multiple processors including integration (SoCBUS) and hardware dependent programming issues. NPU (network processor unit) is also one of our research areas. To support the architecture design, ASIP design tools are continually developed for two purposes; microarchitecture synthesis and source code analysis. Source code analysis tool will explore design space by exposing data and program locality, opportunities of parallelization, and efficient parallel access of scratch pad memories. Applications covered by our research are radio baseband signal processing and other streaming signal processing.
Brief description of finished projects
Novel Generator of Accelerators and Processors
(Per, Wenbiao, and Dake) To design a processor synthesizer to generate RTL codes, assembler, simulator, and compiler without template constriantis of an instruction set
an EU project of FP7 with Infineon, Ericsson, Lund University, TU-Leuven, and IMEC
(Andreas E. Di, Johan, Rizwan, Guoyou, and Dake) To design a programmable platform for radio baseband signal processing of future mobile handset
C-source code profilier for ASIP design
(Dake) To design a tool to speed up understanding of execution behaviors of applications.
A SIMD processor for forward error correction
(Ali and Dake) To design an silicon efficient programmable FEC supporting Viterbi, Turbo, RS, and LDPC.
(Dake and Andreas) A DSP platform for functional acceleration.
(Eric, Anders, and Dake) Algorithm/architecture co-design for multi-standard radio technologies for cost and energy efficiency
(Anders, Eric, and Dake) Algorithm/architecture co-design for multi-standard radio technologies for cost and energy efficiency
(Di, Andreas, Per, Johan, and Dake) To target an efficient and intelligent memory subsystem and its processor
(Tomas, Ulf, and Dake) Latency is the cost of memory in a router. We minimize the total cost in router by minimize de-packaging and routing latency.
(Johan, Di, and Dake) To target on instruction set and an efficient and intelligent memory subsystem with large matrix transpose
(Daniel and Dake) A system on chip connection network with minimum connection and data latency for a system without master.
Informationsansvarig: Anders Nilsson
Senast uppdaterad: 2014-01-28