Research project

Programmable baseband DSP

(Anders Nilsson, Eric Tell, Daniel Wiklund, and Dake Liu)

Introduction

In this project we demonstrate solutions for fully programmable radio baseband processing for Software Defined Radio (SDR). The aim is to design a processor that can support a large number of current and future radio standards and be able to dynamically adapt bandwidth and mobility via software.

The increasing number of radio standards and convergence of functionality in products increases the need for flexibility in baseband processors. At the same time, new demanding applications such as 3G/4G mobile telephony and Digital Video Broadcasting give perfomrance requirements than what cannot be handled by conventional DSP processors. Power consumption continues to be very important in mobile devices.

Architecture principles

The challenge is to reach enough flexibility and performance with a power consumption not much higher than for an ASIC solution. To reach this we focus on four important issues:

• An efficient instruction set for execution of common baseband processing functions on a data path with multiple complex MAC (multiply-accumulate) units.
• An efficient and flexible way of connecting hardware accelerators to the processor core
  • Our architecture allows any number of accelerators to run in parallell and also to synchronize and communicate with each other without interference from the processor core.
• Methodology for determining which functions should be accelerated and which should not
  • The decision is based on how easily the function is implemented in software, how large the hardware cost of the accelerator would be, and to which extent the accelerator can be reused between standards. The reuse is increased by building flexible reconfigurable accelerators.
• Methods for reaching low memory cost, both in terms of memory area and number of memory accesses.
  • We have eliminated the need for intermediate memory storage when data is sent between accelerators. The architecture also allows an entire memory bank to be "handed over" from one unit to another by reconfiguration of the interconnect, thereby eliminating data moves betweeen memories. Efficent instruction encoding and instruction level acceleration reduces progam memory size.

Thanks to a high degree of hardware reuse, efficient hardware acceleration of carefully selected functions, and low memory cost, our silicon area can be less than that of a traditional direct mapped, fixed function ASIC.

Project status

This project has been running since the beginning of 2003. So far we have a demonstrator chip for a fully programmable baseband processor, focused on Wireless LAN aplications (the 802.11a/b/g standards), but which also can handle e.g. the Bluetooth and GSM/GPRS standards. The silicon cost is only 2.9 mm2, which is less than half of other equivalent 802.11a/b/g baseband solutions. The power consumption is also very competitive.

Current and future work

We are currently working on the second generation of our processor. This will support a number of additional standards, such as the latest 3G standards, as well as future 4G and MIMO systems

Publications

Doctor and Licentiate theses

Eric Tell
Design of Programmable Baseband Processors
Ph.D. thesis, Linköping Studies in Science and Technology, Dissertation No. 969, Linköpings universitet, Sep 2005

Anders Nilsson
Design of multi-standard baseband processors
Linköping Studies in Science and Technology, Thesis No. 1173, Linköping, Sweden, June 2005

Journal papers and book chapters

Anders Nilsson and Dake Liu
Handbook of WiMAX
To be published, CRC Press

Anders Nilsson and Dake Liu
Radio design in Nanometer Technologies
ISBN 978-1402048234, Springer 2006

Conference papers 2006

Anders Nilsson, Eric Tell, and Dake Liu
Simultaneous multi-standard support in programmable baseband processors
IEEE PRIME, Otranto, Italy, June 2006

Anders Nilsson and Dake Liu
Multi-standard support in SIMT programmable baseband processors
Proc of the Swedish System-on-Chip Conference (SSoCC), Kolmården, Sweden, May 2006

H Jiao, Anders Nilsson, and Dake Liu
MIPS Cost Estimation for OFDM-VBLAST systems
IEEE Wireless Communications and Networking Conference, Las Vegas, NV, USA, Apr 2006

Conference papers 2005

Anders Nilsson, Eric Tell, Daniel Wiklund, and Dake Liu
Design methodology for memory-efficient multi-standard baseband processors
Asia Pacific Communication Conference, Perth, Australia, Oct 2005

Anders Nilsson, Eric Tell, and Dake Liu
A Programmable SIMD-based Multi-standard Rake Receiver Architecture
European Signal Processing Conference, EUSIPCO, Antalya, Turkey, Sep 2005

Eric Tell, Anders Nilsson, and Dake Liu
A Low Area and Low Power Programmable Baseband Processor Architecture
Proc of the International workshop on SoC for real-time applications, Banff, Canada, July 2005

Eric Tell, Anders Nilsson och Dake Liu
A Programmable DSP core for Baseband Processing
Proc of the IEEE Northeast Workshop on Circuits and Systems (NEWCAS), Quebec City, Canada, Juni 2005

Anders Nilsson, Eric Tell, and Dake Liu
Acceleration in multi-standard baseband processors
Radiovetenskap och Kommunikation, Linköping, Sweden, June 2005

Eric Tell, Anders Nilsson, and Dake Liu
Implementation of a Programmable Baseband Processor
Proc of Radiovetenskap och Kommunikation (RVK), Linköping, Sweden, June 2005

Anders Nilsson, Eric Tell, and Dake Liu
A fully programmable Rake-receiver architecture for multi-standard baseband processors
Networks and Communcation Systems, Krabi, Thailand, May 2005

Dake Liu, Eric Tell, Anders Nilsson, and Ingemar Söderquist
Fully flexible baseband DSP processors for future SDR/JTRS
Western European Armaments Organization (WEAO) CEPA2 Workshop, Brussels, Belgium, March 2005

Conference papers 2004

Dake Liu, Eric Tell, and Anders Nilsson
Implementation of Programmable Baseband Processors
Proc of CCIC, Hangzhou, China, Nov 2004

Anders Nilsson, Eric Tell, and Dake Liu
An accelerator structure for programmable multi-standard baseband processors
WNET2004, Banff, AB, Canada, July 2004

Eric Tell och Dake Liu
A Hardware Architecture for a Multi Mode Block Interleaver
Proc of the International Conference on Circuits and Systems for Communications (ICCSC), Moscow, Russia, Juni 2004

Anders Nilsson and Dake Liu
Processor friendly peak-to-average reduction in multi-carrier systems
Proc of the Swedish System-on-Chip Conference (SSoCC), Båstad, Sweden, March 2004

Conference papers 2003

Eric Tell, Olle Seger och Dake Liu
A Converged Hardware Solution for FFT, DCT and Walsh Transform
Proc of the International Symposium on Signal Processing and its Applications (ISSPA), Paris, France, Vol. I, pp. 609 - 612, Juli 2003