Ph.D. course on FPGA design
Course leadersOscar Gustafsson and Andreas Ehliar
|Feb. 12||15-17||Glashuset||Introduction: Course outline, history, reconfigurable computing||Oscar + Andreas|
|Mar. 1||10.15-12.00||Glashuset||Logic blocks and memory||Andreas|
|Mar. 11||10.15-12.00||Glashuset||DSP blocks, mapping DSP algorithms and arithmetic functions||Oscar|
|Mar. 29||10.15-12.00||Glashuset||I/O and clocking||Andreas|
|Apr. 12||10.15-12.00||Glashuset||Routing network and FPGA architectures||Oscar|
|Apr. 21||13.15-15.00||Glashuset||IP blocks and high-level design||Kent Palmkvist|
|Apr. 30||10.15-12:00||Glashuset||Processors and partial reconfiguration, presentation of tentative projects||Andreas|
CreditsYou will get 4 hp for participating in the lectures and doing the lab. You will get around 4 hp for doing a project, although it is possible to do either a smaller or larger project as well. The project should be documented and presented.
LabThe lab is finally finished. We are sorry about the delay, but we hope that the final lab will be of use to you. Download the lab manual and the lab code. Lab credits: The FFT processor used in the lab is based on VHDL code written by Fahad Qureshi.
Lab updateThere is a bug in xst.mk as the sdf file which contains delay information is not used for the lab.parsim target, only the lab.parsimc target. Download the updated xst.mk if you are planning to use the lab.parsim target.
ProjectThe project should primarily be performed individually, even though it is possible to perform in groups of two or more (the size of the project will then scale accordingly). Preferably the project should be relevant to your research.
The following deadlines applies to be able to have several presentations at once:
|August 30||September 3(?)|
|Petter||Parallel adder chains||-||-|
|Farooq||Pipelined constant multipliers||-||-|
|Ameya||Cache as a hard block||-||-|
|Olof||Floating point as a hard block||-||-|
|Mudassar||JTAG for TAP applications||-||-|
|Carl||Redesign of the USRP sample rate conversion||-||-|
|Zaka||Implementation of FRM filters||-||-|
|Asad||Implementation of sparse FIR filters||-||-|
|Somasekar||Pipelined reduction trees for large multipliers||-||-|
Other resourcesHere are a few resources that could be of interest to participants in this course. Especially the first entry is highly recommended.
- FPGA Architecture: Survey and Challenges - I. Kuon, R. Tessier and J. Rose
- Advanced FPGA Design - Architecture, Implementation, and Optimization - Steve Kilts
- Publications by Andraka Consulting Group
- The archives of the Usenet group comp.arch.fpga has a lot of hidden gems.
- Finally, I hope that the following document may be of interest to someone... Performance driven FPGA design with an ASIC perspective - Andreas Ehliar
Conferences and journalsThis is a list of some conferences and journals of interest for this course. You might want to think about selecting a project which could be relevant as a possible submission to one of them.
- FPGA World 2010, Copenhagen, Aug. 30, deadline June 1.
- FPT 2010, Beijing, Dec. 8-10, deadline June 1 2010.
- FPGA 2011, Monterey, Feb., expected deadline autumn 2010.
- FPL 2011, expected deadline spring 2011.
- ARC 2011, expected deadline autumn 2010.
- ACM Transactions on Reconfigurable Technology and Systems
- International Journal of Reconfigurable Computing
Last Changed Date: 2010-07-20 15:48:29 +0200 (Tue, 20 Jul 2010) Last update by: Andreas Ehliar
Informationsansvarig: Anders Nilsson
Senast uppdaterad: 2014-01-30