TSEA26
Design of Embedded DSP Processors

Course page for 2011

Course Responsible: Andreas Ehliar

Computer Engineering, ISY

Linköpings Universitet

Phone +46-13-28 8956

Email: ehliar@isy.liu.se

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The Goal of the Course

To give students design experiences in embedded DSP processors and DSP firmware, as well as system integration.

Pre-requisites/Teaching Language

• Fundamentals of Signal Processing
• Fundamentals of Computer Hardware and Architecture
• TSEA19/20
• Some of the labs require a basic understanding of VHDL or Verilog
• The teaching language will be English

Text book

Dake Liu

Embedded DSP Processor Design, Application Specific Instruction set Processors

Elsevier (Morgan Kaufmann), ISBN 9780123741233, June,2008

The book is available from two bookstores in Campus Valla. It is also available from for example www.amazon.com (search book, type in the author's name Dake Liu) or click here.

We also have an errata page for the book here.

Reading instructions

The following chapters in the book are are included in the course:
1, 2*, 3.1, 3.2, 3.3*, 4, 5, 6.1, 7.1*, 7.2*, 7.3*, 7.4, 7.6, 8.1, 8.5, 8.7, 9.1, 10*, 11*, 12*, 13*, 14* (not 14.4.5 and 14.4.6), 15.1, 15.2*, 15.4, 15.5, 16.1, 18.1-18.3

Chapters marked with an asterisk are the focus of the course

Organization and Requirements

There are 3 hp from the laboratory work and 3 hp from the written examination. Instructions on both the homework and labs will be given in tutorials. All lab work will be allocated in the computer rooms Olympen and Egypten of ISY in B-Huset. Please check the lab time you have registered for each lab and be there on time. In order to take the labs, you have to be registered to the course first. Unregistered students will not be allowed to the labs due to limited seats.

Careful reading of lab introduction and instruction is required before participating each lab. Your lab instructors have the right to disqualify your lab work if you come to the lab without any pre-reading.

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Lectures

Rough reading instructions are included for each lecture. (See reading instructions above for more exact information about the exact contents of the course.

• Lecture 1: Introduction and some numerical representation(Ch 1)
• Lecture 2: Numerical representations and an introduction to Junior (Ch 2, a little Ch 5)
• Lecture 3: Junior (Ch 5)
• Lecture 4: DSP architecture and ASIP Design flow (Ch 3, Ch 4, Ch 7)
• Lecture 5: Microarchitecture, RF, and ALU (Ch 10, Ch 11, Ch 12)
• Lecture 6: ALU and MAC (Ch 12, Ch 13) (The MAC example from lecture 6)
• Lecture 7: MAC and Control path (Ch 13 and Ch 14) (The MAC example from lecture 7)
• Lecture 8: Control path and Memory sub system (Ch 14 and Ch 15)
• Lecture 9: Memory sub system, Programming toolchain and simulator (Ch 11)
• Lecture 10: Modelling of DSP applications and firmware development (Ch 18)
• Lecture 11: Verification, exam hints, and introduction to the design challenge

Tutorials

Tutorials will be added to this page around one day before or after the tutorial is given. For most of the tutorials exercise solutions are available, either in the tutorial slides or as a separate file.

• Tutorial-1 (Micro-architecture and Finite Length) (2011)
• Tutorial-2 exercises (2011)
• Tutorial-2 (ALU Design) (2011)
• Tutorial-3 exercises (2011)
• Tutorial-3 exercise solutions (2011)
• Tutorial-3 (MAC Design) (2011)
• Tutorial-4 exercises (2011)
• Tutorial-4 exercise solutions (2011)
• Tutorial-4 (PC-FSM Design) (2011)
• Tutorial-5 exercises (2011)
• Tutorial-5 solutions (2011)
• Tutorial-6 exercises (2011)
• Tutorial-6 solutions (2011)

Old material

Here is some tutorial material from last time the course was given.

• Tutorial-5 (AGU Design) (2010)
• Tutorial-6 (Prototyping ASIP Instructions) (2010)

Labs

Don't forget to sign up for the labs using the electronic lab registration.

LAB Manual in Parts

• Ch-0 (Introduction)
• Ch-1 (Lab1-Firmware)
• Ch-2 (Lab2-Datapath) (Minor update on 2011-09-21)
• Ch-3 (Lab3-Program Flow) (Updated on 2011-09-22)
• Ch-4 (Lab4-Prototyping ASIP Instructions)

Documentation of the Senior DSP

• Assembler and Simulator User Manual of Senior DSP
• Instruction Set Manual of Senior DSP

Source Code for Labs

• Lab 1
• Lab 2-3 (with VHDL bugfix applied 2011-09-20)
• Updated rtl/id_pipeline_logic.v - Please replace your current version of id_pipeline_logic.v with this one instead to avoid a bug caused by an undetected structural hazard (2011-09-27)
• Lab 4

Lab errata

This is our internal TODO list for the labs:

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Design challenge

If you want some practice before the exam, the DSP processor design challenge is a good place to start.

Old exams

For most of these exams I have included a solution proposal. I've tried to solve each exercise in a fairly realistic fashion. That is, even if the exam allows you to solve an exercise in a fairly non-efficient manner (e.g. by using a very long critical path), I've tried to avoid such "unrealistic" solutions here. (Or I might provide two alternative solutions, one "simple" and one realistic.) It is my hope that you might be able to learn a new trick or two by studying these solution proposals. (But don't worry if you wouldn't come up with these tricks yourself on the exam, there are usually many other ways to solve most of these exercises.)

• 2009-10-22 (Solutions)
• 2010-01-14 (Solutions)
  Errata: Question 3.a should be worth 12 points, not 11, making question 3 worth 15 points in total instead of 14.
• 2010-08-27 (Solution proposal not available as only 6 people participated in this exam.)
• 2010-10-23 (Solutions))
  Errata: Question 1: OP7 should be PC = POP() instead of POP(PC). Question 1 should also have an OP8 and OP9 instead of two OP8.
• 2011-01-12 (Solutions)
  Errata: Question 5: Part C-E should have been labelled part B-D.
• 2011-08-23 (Solutions)
• 2011-10-22 (Solutions)

I also have a short FAQ regarding the written exam.

Staff

Name	Phone	Room	Email	Responsibility
Andreas Ehliar	8956	3B:522	ehliar@isy.liu.se	Course responsible, lectures
Olle Seger	2159	3B:546	olles@isy.liu.se	Tutorials
Jian Wang	2601	3B:550	jianw@isy.liu.se	Tutorials, labs
Andreas Karlsson	2601	3B:550	andreask@isy.liu.se	Labs
Joar Sohl	1363	3B:529A	joar@isy.liu.se	Labs
Ylva Jernling	2648	3B:542	ylva@isy.liu.se	Administration

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